1. Field of the Invention
The present invention relates to an improvement in a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
[A] In recent years, with an increase in the integration density of semiconductor devices, the number of wiring layers formed on a substrate has increased to five to six. In order to prevent an increase in the number of wiring layers formed on a substrate, methods of burying wiring layers in the substrate are proposed. As a method of burying wiring layers in a substrate, part of the invention disclosed in Jpn. Pat. Appln. KOKAI Publication No. 63-263758 will be described below.
FIGS. 1 to 9A are perspective views showing the method disclosed in Jpn. Pat. Appln. KOKAI Publication No. 63-263758. In this method, first of all, as shown in FIG. 1, a silicon oxide film (SiO.sub.2) 202, a silicon nitride film (Si.sub.3 N.sub.4) 203, and a silicon oxide film (CVD-SiO.sub.2) 204 are sequentially formed on a p-type silicon substrate 201. These films are patterned, and a deep trench 225 is formed in the substrate 201 by a dry etching method.
As shown in FIG. 2, a silicon oxide film 205 is formed on the side and bottom surfaces of the deep trench 225 by thermal oxidation. A polysilicon film 206 doped with arsenic (As) is formed on the entire surface of the resultant structure. The polysilicon film 206 is etched back to a predetermined position by the dry etching method to form a first wiring layer 206'.
Subsequently, as shown in FIG. 3, the silicon oxide film 205 is etched by a wet etching method using the first wiring layer 206' as a mask. At this time, the silicon oxide film 204 on the substrate 201 is completely removed. A polysilicon film 207 is formed on the entire surface of the resultant structure.
As shown in FIG. 4, the polysilicon film 207 is selectively etched to a predetermined position to form a connecting layer 207' between the first wiring layer 206' and a drain diffusion layer (formed in the subsequent step) of a transistor. Thereafter, the silicon nitride film 203 is removed by etching. A silicon oxide film 208 is formed on the resultant structure by thermal oxidation. At the same time, since arsenic is diffused from the first wiring layer 206' to the substrate 201 via the connecting layer 207', an n.sup.+ -type drain diffusion layer 210 is formed on the surface of the substrate 201 which is a side wall of the deep trench 225. An undoped polysilicon film 209 is formed on the entire surface of the resultant structure. In addition, the polysilicon film 209 is left on the upper portion of the deep trench 225 by an entire surface etching method.
As shown in FIG. 5, a silicon oxide film 211 is formed on the entire surface of the resultant structure. The silicon oxide film 211 is then patterned. A shallow trench 212 shallower than the deep trench 225 is formed to be perpendicular to the deep trench 225 by the dry etching method using the silicon oxide film 211 as a mask. Note that the depth of the shallow trench 212 is set such that the drain diffusion layer 210 on each side wall of the deep trench 225 is exposed.
As shown in FIG. 6, a silicon nitride film (Si.sub.3 N.sub.4) 213 is formed on the entire surface of the resultant structure. The silicon nitride film 213 is then patterned. The silicon nitride film 213 is left to cover the channel portion of a transistor.
As shown in FIG. 7, a silicon oxide film 214 is formed by thermal oxidation. When the silicon nitride film 213 is removed, a field oxide film (silicon oxide film 214) is formed on the portion which is not covered with the silicon nitride film 213. In addition, a gate insulating film 215 is formed on the portion which is covered with the silicon nitride film 213.
As shown in FIG. 8, a tungsten silicide film is formed on the entire surface of the resultant structure. In addition, anisotropic dry etching is performed to leave the tungsten silicide film on only a side wall of the shallow trench 212, thus forming a gate electrode 217 of the transistor. Thereafter, a silicon oxide film (CVD-SiO.sub.2) 218 is buried in the shallow trench 212.
As shown in FIG. 9, arsenic ions are implanted in the resultant structure at, for example, an acceleration voltage of about 100 keV and a dose of about 1.times.10.sup.16 cm.sup.-2. Thereafter, the resultant structure is annealed to form an n.sup.+ -type source diffusion layer 216 in the surface portion of the substrate 201 which is covered with the silicon nitride film 213. A contact hole 223 is formed in the silicon oxide film 214 to reach the source diffusion layer 216. After a metal wiring pattern 220 is formed, a silicon oxide film 221 and a silicon nitride film 222 are formed on the resultant structure by a plasma CVD method.
In the above-described manufacturing method as shown in FIG. 9A, the element (transistor) connected to the first wiring layer 206 cannot be structurally formed right above the first wiring layer 206. For this reason, the element is formed on a side of the first wiring layer 206.
In this method, for example, a wiring layer cannot be formed right under the gate electrode of a transistor, or a wiring layer crossing the channel portion of the transistor cannot be formed. Therefore, the degree of freedom is low in terms of patterns. In addition, since two trenches must be formed, the manufacturing process is complicated, resulting in an increase in cost.
[B] There is a growing trend toward larger capacities in dynamic RAMs (to be referred to as DRAMs hereinafter). Therefore, various proposals have been made to maximize the capacitor area of a memory cell in a limited region on a semiconductor substrate. As one of such proposals, a stacked capacitor is known.
A method of manufacturing a conventional DRAM having a stacked capacitor will be described below.
FIGS. 10 to 21 show the method of manufacturing the conventional DRAM having the stacked capacitor.
First of all, as shown in FIG. 10, a silicon oxide film and a silicon nitride film are formed on a p-type silicon substrate 301. A photoresist is formed on the silicon nitride film. The photoresist is then patterned.
The silicon nitride film is etched by the dry etching method using the photoresist as a mask. Thereafter, a p-type impurity (e.g., boron) is implanted in the substrate 301 by using the silicon nitride film as a mask.
When thermal oxidation is performed after the photoresist is removed, a p-type inversion preventing diffusion layer 302 is formed in the substrate 301, and a field oxide film 302 is formed on the inversion preventing diffusion layer 302. The silicon oxide film and the silicon nitride film are then completely removed.
As shown in FIGS. 11 and 12, a gate oxide film 304 of a transistor is formed in an element region by thermal oxidation. A polysilicon film doped with, e.g., phosphorous is formed on the resultant structure by an LPCVD method, and a silicon nitride film (Si.sub.3 N.sub.4) 305 is formed on the polysilicon film.
A photoresist is newly formed on,the silicon nitride film 305. The photoresist is then patterned. The silicon nitride film 305 and the polysilicon film are etched by the dry etching method using the photoresist as a mask. As a result, a gate electrode 306 of the transistor is formed.
After the photoresist is removed, an n-type impurity (e.g., arsenic) is implanted in the substrate 301 by using the silicon nitride film 305 and the gate electrode 306 as masks. Thereafter, thermal oxidation is performed to form a silicon oxide film 307 on each side surface of the gate electrode 306 and also form an n-type source region 308a and an n-type drain region 308b of the transistor in the substrate 301.
As shown in FIG. 13, a silicon nitride film (Si.sub.3 N.sub.4) 309 is formed by the LPCVD method. The silicon nitride film 309 is etched by the dry etching method to be left on only each side wall surface of the gate electrode 306.
A silicon oxide film 310 is formed on the resultant structure by the LPCVD method. A photoresist is newly formed on the silicon oxide film 310. The photoresist is then patterned. The silicon oxide film 310 is etched by the dry etching method to form a contact hole 311 reaching the source region 308a. Thereafter, the photoresist is removed.
As shown in FIGS. 14 and 15, a polysilicon film doped with, e.g., phosphorous is formed by the LPCVD method.
A photoresist is newly formed on the polysilicon film. This photoresist is then patterned. The polysilicon film is etched by the dry etching method using the photoresist as a mask to form a storage electrode (storage node) 312 of the capacitor of a memory cell.
Note that this storage electrode 312 is not formed on the drain region 308b of the transistor of the memory cell.
FIGS. 16 and 17, after the photoresist is removed, a capacitor insulating film 313, e.g., a multilayered film (NO film) composed of silicon nitride and silicon oxide layers, is formed on the resultant structure. Furthermore, a polysilicon film doped with, phosphorous is formed by the LPCVD method.
A photoresist is newly formed on the polysilicon film. The photoresist is then patterned. The polysilicon film and the capacitor insulating film 313 are etched by the dry etching method using the photoresist as a mask to form a plate electrode 314 of the capacitor of the memory cell.
Note that this plate electrode 314 is not formed on the drain region 308b of the transistor of the memory cell.
After this process, the photoresist is removed.
As shown in FIG. 18, a silicon oxide film 315 is formed by the LPCVD method. A photoresist is newly formed on the silicon oxide film 315. The photoresist is then patterned. The silicon oxide film 315 is etched by the dry etching method using the photoresist as a mask to form a contact hole 316. Thereafter, the photoresist is removed.
An n-type impurity, e.g., arsenic, is implanted in the substrate 301 at the bottom portion of the contact hole 316 by an ion implantation method, and the resultant structure is annealed in a nitrogen atmosphere. As a result, an n.sup.+ -type diffusion layer 317 is formed.
As shown in FIGS. 19 and 20, a tungsten (W) film is formed by, e.g., a CVD method. A photoresist is newly formed on the tungsten film. The photoresist is then patterned. The tungsten film is etched by the dry etching method using the photoresist as a mask to form a bit line 318 which linearly extends. Thereafter, the photoresist is removed.
As shown in FIG. 21, a silicon oxide film 319 is formed by the LPCVD method. A contact hole is formed in a predetermined portion of the silicon oxide film 319. A barrier metal (e.g., a multilayered film composed of titanium and titanium nitride layers) 320 and an aluminum.silicon (Al.Si) film 321 are formed on the silicon oxide film 319 by a sputtering method.
A photoresist is newly formed on the aluminum.silicon film 321. The photoresist is then patterned. The aluminum.silicon film 321 and the barrier metal 320 are etched by the dry etching method using the photoresist as a mask to form a wiring layer. Thereafter, the photoresist is removed.
In the above-described manufacturing method, the storage electrode 312 of the capacitor of the memory cell cannot be located on the drain region 308b of the memory cell transistor. This is because the contact hole 316 is formed in this region to bring the bit line 318 into contact with the drain region 308b.
That is, in the DRAM formed by this manufacturing method, since a certain alignment margin is required between a capacitor electrode and a bit line contact region, the capacitor area cannot be sufficiently increased.
FIGS. 22 to 25 show a method of manufacturing a conventional DRAM having a stacked capacitor, which method is designed to increase the capacitor area.
First of all, as shown in FIG. 22, a p-type inversion preventing diffusion layer 302 and a field oxide film 303 are formed in a p-type substrate 301. A gate oxide film 304 of a memory cell transistor is formed in an element region. A gate electrode 306 is formed on the gate oxide film 304.
After an n-type source region 308a and an n-type drain region 308b of the transistor are formed in the substrate 301, a silicon oxide film 310 is formed on the entire surface of the substrate 301 by the LPCVD method. In addition, the silicon oxide film 310 is etched to form a contact hole 311 reaching the source region 308a.
As shown in FIGS. 23 and 24, a polysilicon film doped with, e.g., phosphorous is formed by the LPCVD method. Subsequently, a silicon oxide film 322 is formed on the polysilicon film by the LPCVD method.
A photoresist is formed on the silicon oxide film 322. The photoresist is then patterned. The silicon oxide film 322 and the polysilicon film are etched by the dry etching method using the photoresist as a mask to form a storage electrode (storage node) 312a of the memory cell.
Note that the storage electrode 312a is not formed on the drain region 308b of the transistor of the memory cell.
After the photoresist is removed, a polysilicon film doped with, e.g., phosphorous is formed on the resultant structure. This polysilicon film is etched by the dry etching method to form a storage electrode (storage node) 312b on side surfaces of the storage electrode 312a and the silicon oxide film 322.
Subsequently, as shown in FIG. 25, after the silicon oxide film 322 is removed, a capacitor insulating film 313, e.g., a multilayered film (NO film) composed of silicon nitride and silicon oxide layers, is formed on the resultant structure. Furthermore, a polysilicon film doped with, e.g., phosphorous is formed by the LPCVD method.
A photoresist is newly formed on this polysilicon film. The photoresist is then patterned. The polysilicon film and the wafer capacitor insulating film 313 are etched by the dry etching method to form a plate electrode 314 of the capacitor of the memory cell.
Note that this plate electrode 314 is not formed on the drain region 308b of the transistor of the memory cell.
After the photoresist is removed, a silicon oxide film 315 is formed on the resultant structure by the LPCVD method. A contact hole 316 is formed in the silicon oxide film 315, and an n.sup.+ -type diffusion layer 317 is formed in the substrate 301 at the bottom portion of the contact hole 316. A tungsten (W) film is formed on the resultant structure by the CVD method. This tungsten film is patterned to form a bit line 318.
A silicon oxide film 319 is formed by the LPCVD method, and a contact hole is formed in a predetermined portion of the silicon oxide film 319. A barrier metal (e.g., a multilayered film composed of titanium and titanium nitride layers) 320 and an aluminum.silicon (Al.Si) film 321 are formed on the silicon oxide film 319 by the sputtering method. The aluminum.silicon film 321 and the barrier metal 320 are patterned to form a wiring layer.
In the above-described manufacturing method, since the storage electrode 312 of the capacitor of the memory cell is formed in the form of a crown, the capacitor area can be increased.
In this method, however, the process of manufacturing the capacitor of a memory cell is complicated. In addition, the aspect ratio of the contact hole 316 needs to be large to bring the drain region 308b and the bit line 318 of the memory cell transistor into contact with each other.
As described above, in order to prevent an increase in the number of wiring layers to be formed on a substrate, methods of burying wiring layers in the substrate have been proposed. However, these methods are not satisfactory because the degree of freedom is low in terms of patterns, and the manufacturing process is complicated.
Furthermore, in the DRAM having the stacked capacitor, in order to ensure reliability, it is required that a reduction in capacitor area be prevented regardless of the growing trend toward larger capacities. This requirement must be satisfied.